Writing Target Code that Should Not Be Built for CPU-Only Execution

This topic only applies to IA-32 architecture targeting Intel® Graphics Technology. Intel® Graphics Technology is a preview feature.

You can write code that should not be built when the target is a CPU-only executable.

By default, the compiler defines the macro __INTEL_OFFLOAD. You can write code within an #ifdef __INTEL_OFFLOAD section when the source code is customized for running on the target.

For example, you can use this macro to check that the code was built with the negative form of the Qoffload compiler option, or to switch between an offload parallel loop, using #pragma parallel_loop, which is not parallelized on the host, and an Intel® Cilk™ Plus-style parallel loop, using _cilk_for, which is not supported on Intel® Graphics Technology.

Example

The section for the host compiler works only when you compile with the negative form of the Qoffload compiler option.

#ifdef __INTEL_OFFLOAD
        cout << "\nThis program is built with __INTEL_OFFLOAD.\n"
<< "The target(gfx) code will be executed on target if it is available\n";
#else
        cout << "\nThis program is built without __INTEL_OFFLOAD\n";
<< "The target(gfx) code will be executed on CPU only.\n";
#endif

Note

This code can only be used in the host code because code for Intel® Graphics Technology does not support this kind of I/O.

Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804