Get Link | Sync TOC
User and Reference Guide for the Intel® C++ Compiler 14.0
Legal Information
Introducing the Intel® C++ Compiler
Feature Requirements
Getting Help and Support
Related Information
Notational Conventions
Getting Started
Using Microsoft Visual Studio*
Creating a Simple Project
Using the Intel® C++ Toolbar (VS 2008)
Using the Intel® C++ Compiler (VS 2010)
Using the Intel® C++ Compiler (VS 2008)
Building Your Intel® C++ Project
Changing the Selected Compiler (VS 2010)
Changing the Selected Compiler (VS 2008)
Switching Back to the Visual C++* Compiler
Selecting a Configuration
Specifying a Target Platform
Specifying Directory Paths (VS 2010)
Specifying Directory Paths (VS 2008)
Using Property Pages (VS 2010)
Using Property Pages (VS 2008)
Using Intel® Performance Libraries (VS 2010)
Using Intel® Performance Libraries (VS 2008)
Changing the Selected Intel® Performance Libraries (VS 2010)
Changing the Selected Intel® Performance Libraries (VS 2008)
Using Guided Auto Parallelism in the Microsoft Visual Studio* IDE
Using Code Coverage in the Microsoft Visual Studio* IDE
Using Profile Guided Optimization in the Microsoft Visual Studio* IDE
Using the Performance Guide in the Microsoft Visual Studio* IDE
Using Static Analysis in the Microsoft Visual Studio* IDE
Uninstalling the Intel® C++ Compiler (VS 2008)
Custom Build Rule (VS 2008)
Performing Parallel Project Builds
Dialog Box Help
Options: Compilers dialog box (VS 2010)
Options: Compilers dialog box (VS 2008)
Options: General dialog box (VS 2008)
Select Build Components dialog box (VS 2008)
Use Intel® C++ dialog box (VS 2010)
Use Intel® C++ dialog box (VS 2008)
Options: Intel Performance Guide dialog box
Performance Guide: Use Intel® C++ Compiler dialog box
Performance Guide: Select a Configuration dialog box
Performance Guide: Options Selector dialog box
Options: Intel® Performance Libraries dialog box (VS 2010)
Options: Intel® Performance Libraries dialog box (VS 2008)
Options: Guided Auto Parallelism dialog box
Profile Guided Optimization dialog box
Options: Profile Guided Optimization dialog box
Configure Analysis dialog box
Options: Converter dialog box (VS 2010)
Static Analysis Create Configuration dialog box
Static Analysis Prepare Projects page (VS 2008)
Code Coverage dialog box
Options: Code Coverage dialog box
Code Coverage Settings dialog box
Using Xcode*
Creating an Xcode* Project
Selecting the Intel Compiler
Building the Target
Setting Compiler Options
Running the Executable
Building a Universal Binary from the Command line
Using Intel® Performance Libraries
Using Eclipse*
Overview: Eclipse* Integration
Starting Eclipse*
Adding the Compiler and Debugger to Eclipse*
Multi-version Compiler Support
Using Cheat Sheets
Creating a Simple Project
Creating a New Project
Adding a C Source File
Setting Options for a Project or File
Excluding Source Files from a Build
Building a Project
Running a Project
Intel® Error Parser
Make Files
Project Types and Makefiles
Exporting Makefiles
Updating a Project to Use the Intel® C++ Compiler
Using Intel® Performance Libraries
Using Guided Auto Parallelism in the Eclipse* IDE
Reusing Guided Auto Parallelism Configurations
Dialog Box Help
Options: Guided Auto Parallelism dialog box
Guided Auto Parallelism Invocation dialog box
Using the Command Line
Using the compilervars File to Specify Location of Components
Invoking the Intel® C++ Compiler
Understanding File Extensions
Using Makefiles to Compile Your Application
Using Compiler Options
Specifying Include Files
Specifying Object Files
Specifying Assembly Files
Modifying Projects to Use a Selected Compiler from the Command Line
Batch Mode (VS 2008)
Key Features
Intel® Graphics Technology
Intel® Graphics Technology Overview
Programming for Intel® Graphics Technology
Overview: Heterogeneous Programming
Initiating an Offload on Intel® Graphics Technology
Writing Target-Specific Code for Intel® Graphics Technology
Vectorizing for Intel® Graphics Technology
Managing Memory Allocation on the Target for Pointer Variables
Memory Access Considerations
Writing Target Code that Should Not Be Built for CPU-Only Execution
Restrictions on Offloaded Code for Intel® Graphics Technology
Allocating Variables and Arrays Efficiently
Placing Variables and Functions on the Processor Graphics
Reduction Functions for Intel® Graphics Technology
Optimizing Iterative Offload
Fully Using Parallelism Specific to Intel® Graphics Technology
Runtime Control, Diagnostics, and Monitoring
Logging Offload Behavior
Controlling Thread Count
Controlling Backup Execution on the CPU
Offload Timers for Intel® Graphics Technology
Intel® MIC Architecture
Overview: Intel® MIC Architecture
Programming for Intel® MIC Architecture
Overview: Heterogeneous Programming
Dealing with Multiple Coprocessors in a System
Offload Using a Pragma
Overview: Using a Pragma
Initiating an Offload
Placing Variables and Functions on the Coprocessor
Managing Memory Allocation for Pointer Variables
Writing Target-Specific Code Using a Pragma
Writing Code that Should Not Be Built for CPU-Only Execution
Allocating Memory for Parts of Arrays
Moving Data from One Variable to Another
Restrictions on Offloaded Code Using a Pragma
Offload Using Shared Virtual Memory
Overview: Using Shared Virtual Memory
Using Shared Memory
_Cilk_offload (C/C++ Keyword)
_Cilk_shared (C/C++ Keyword)
Rules for Using _Cilk_shared and _Cilk_offload
Synchronization Between the CPU and the Target
Writing Target-Specific Code with _Cilk_offload
Restrictions on Offloaded Code Using _Cilk_shared/_Cilk_offload
Restrictions When Programming on Windows* OS for Intel® MIC Architecture
About Asynchronous Computation
About Asynchronous Data Transfer
Applying the target Attribute to Multiple Declarations
Controlling the Coprocessor's Execution Environment
Overview: Controlling the Coprocessor's Execution Environment
Setting Environment Variables on the CPU to Modify the Coprocessor's Execution Environment
Environment Variables for I/O Proxy Control for Offloaded Code
Calling Functions on the CPU to Modify the Coprocessor's Execution Environment
Using Libraries in Offloaded Code
About Creating Offload Libraries with xiar and xild
Special Cases
OpenMP* Considerations
OpenMP* Defaults
OpenMP* Affinity Specifications
Balanced Affinity Type
Setting the Number of OpenMP* Threads on the Coprocessor
Data Alignment for Intel® MIC Architecture
Measuring Timing and Data in Offload Regions
__Offload_report
Calling exit() From an Offload Region
Building for Intel® MIC Architecture
Setting Stack Size on Coprocessors
About Building Native Intel® MIC Architecture Applications
Appending Archiver Options for Creating Libraries
Appending Linker Options
Logging Stdout and Stderr from Offloaded Code
Automatic Parallelization
Auto-Parallelization Overview
Enabling Auto-parallelization
Programming with Auto-parallelization
Enabling Further Loop Parallelization for Multicore Platforms
Language Support for Auto-parallelization
Guided Auto Parallelism
Guided Auto Parallelism Overview
Using Guided Auto Parallelism
Guided Auto Parallelism Messages
Guided Auto -Parallelism Messages Overview
GAP Message (Diagnostic ID 30506)
GAP Message (Diagnostic ID 30513)
GAP Message (Diagnostic ID 30515)
GAP Message (Diagnostic ID 30519)
GAP Message (Diagnostic ID 30521)
GAP Message (Diagnostic ID 30522)
GAP Message (Diagnostic ID 30523)
GAP Message (Diagnostic ID 30525)
GAP Message (Diagnostic ID 30526)
GAP Message (Diagnostic ID 30528)
GAP Message (Diagnostic ID 30531)
GAP Message (Diagnostic ID 30532)
GAP Message (Diagnostic ID 30533)
GAP Message (Diagnostic ID 30534)
GAP Message (Diagnostic ID 30535)
GAP Message (Diagnostic ID 30536)
GAP Message (Diagnostic ID 30537)
GAP Message (Diagnostic ID 30538)
GAP Message (Diagnostic ID 30753)
GAP Message (Diagnostic ID 30754)
GAP Message (Diagnostic ID 30755)
GAP Message (Diagnostic ID 30756)
GAP Message (Diagnostic ID 30757)
GAP Message (Diagnostic ID 30758)
GAP Message (Diagnostic ID 30759)
GAP Message (Diagnostic ID 30760)
Automatic Vectorization
Automatic Vectorization Overview
Programming Guidelines for Vectorization
Using Automatic Vectorization
Vectorization and Loops
Loop Constructs
User-mandated or SIMD Vectorization
Function Annotations and the SIMD Directive for Vectorization
Clang Support
Clang Support Overview
High-Level Optimization (HLO)
High-Level Optimizations (HLO) Overview
Intel® Cilk™ Plus
Introduction
Introduction
Getting Started
Summary of Intel® Cilk™ Plus Language Features
Convert a C/C++ Program
Build, Run and Debug an Intel® Cilk™ Plus Program
Set Worker Count
Serialization
Debugging Strategies
Intel® Cilk™ Plus Keywords
Introduction to Keywords
cilk_spawn
cilk_sync
cilk_for
Intel® Cilk™ Plus Execution Model
Key Concepts
Strands
Pedigrees
Work and Span
Mapping Strands to Workers
Exception Handling
Reducers
Introduction to Reducers
Using Reducers - A Simple Example
How Reducers Work
Safety and Performance Considerations
Reducer Library
Using Reducers - More Examples
Advanced Topic: How to Write a New Reducer
Holders
Introduction to Holders
Using Holders - An Example
Holder Syntax
Operating System Considerations
Using Other Tools with Intel® Cilk™ Plus Programs
General Interaction with OS Threads
Microsoft Foundation Classes and Intel® Cilk™ Plus Programs
Intel® Cilk™ Plus Run Time System API
Introduction to the Run Time System API
__cilkrts_bump_loop_rank
__cilkrts_bump_worker_rank
__cilkrts_end_cilk
__cilkrts_get_nworkers
__cilkrts_get_pedigree
__cilkrts_get_total_workers
__cilkrts_get_worker_number
__cilkrts_init
__cilkrts_set_param
Understanding Race Conditions
Data Races
Resolving Data Races
Introduction to Using Locks
Considerations for Using Locks
Locks Cause Determinancy Races
Deadlocks
Lock Contention
Holding a Lock Across a Strand Boundary
Performance Considerations for Intel® Cilk™ Plus Programs
Performance Considerations for Intel® Cilk™ Plus Programs
Granularity
Optimize the Serial Program
Timing Programs and Program Segments
Common Performance Pitfalls
Cache Efficiency and Bandwidth
False Sharing
Memory Allocation Bottlenecks
Extensions for Array Notation
C/C++ Extensions for Array Notations Overview
C/C++ Extensions for Array Notations Programming Model
SIMD-Enabled Functions
Glossary
Intel® Math Library
Overview: Intel® Math Library
Using Intel® Math Library
Math Functions
Function List
Trigonometric Functions
Hyperbolic Functions
Exponential Functions
Special Functions
Nearest Integer Functions
Remainder Functions
Miscellaneous Functions
Complex Functions
C99 Macros
Interprocedural Optimization (IPO)
Interprocedural Optimization (IPO) Overview
Using IPO
IPO-Related Performance Issues
IPO for Large Programs
Understanding Code Layout and Multi-Object IPO
Creating a Library from IPO Objects
Requesting Compiler Reports with the xi* Tools
Inline Expansion of Functions
Inline Function Expansion
Compiler Directed Inline Expansion of Functions
Developer Directed Inline Expansion of User Functions
OpenMP* Support
OpenMP* Support Overview
OpenMP* Source Compatibility and Interoperability with Other Compilers
Using OpenMP*
Parallel Processing Model
Worksharing Using OpenMP*
Controlling Thread Allocation on the Intel® Xeon Phi™ coprocessor
OpenMP* Pragmas and Clauses Summary
OpenMP* Library Support
OpenMP* Run-time Library Routines
Intel Extension Routines to OpenMP*
OpenMP* Support Libraries
Using the OpenMP* Libraries
Thread Affinity Interface
OpenMP* Advanced Issues
OpenMP* Examples
Supporting C++11 Lambda Feature
Using Lambda Expressions with Intel® Threading Building Blocks
Intel's C++ lambda extensions
Introduction
Details on Using Lambda Expressions in C++
Understanding Lambda-Capture
Lambda Function Object
Performance Guide
Performance Guide Overview
Performance Guide Setup and Workflow
Starting the Performance Guide
Using the Performance Guide Workflow Window
Using the Performance Guide Run All Steps Mode
Using the Performance Guide Check Performance Measurements Window
Other Performance-Related Tools
Pointer Checker
Pointer Checker Overview
Pointer Checker Feature Summary
Using the Pointer Checker
Checking Bounds
Checking for Dangling Pointers
Checking Arrays
Working with Enabled and Non-Enabled Modules
Storing Bounds Information
Passing and Returning Bounds
Checking Run-Time Library Functions
Writing a Wrapper
Checking Custom Memory Allocators
Checking Multi-Threaded Code
How the Compiler Defines Bounds Information for Pointers
Finding and Reporting Out-of-Bounds Errors
Processor Targeting
Targeting Processors Manually
Profile-Guided Optimization (PGO)
Profile-Guided Optimizations Overview
Profile an Application
Profile Function or Loop Execution Time
PGO Tools
PGO Tools Overview
profmerge and proforder Tools
Using Function Order Lists, Function Grouping, Function Ordering, and Data Ordering Optimizations
Comparison of Function Order Lists and IPO Code Layout
PGO API Support
API Support Overview
Resetting Profile Information
Dumping Profile Information
Interval Profile Dumping
Resetting the Dynamic Profile Counters
Dumping and Resetting Profile Information
Getting Coverage Summary Information on Demand
Static Analysis
Static Analysis Overview
Using Static Analysis
Creating and Using Build Specification Files
Tools
code coverage Tool
test prioritization Tool
Compiler Option Mapping Tool
Intel® MIC Architecture Image Extraction Tool
Compatibility and Portability
Conformance to the C/C++ Standards
GCC* Compatibility and Interoperability
Microsoft* Compatibility
Microsoft* Visual C++* Compatibility
Precompiled Header Support
Compilation and Execution Differences
Declaration in Scope of Function Defined in a Namespace
Enum Bit-Field Signedness
Portability
Porting from the Microsoft* Compiler to the Intel® Compiler
Overview: Porting from the Microsoft* Compiler to the Intel® Compiler
Modifying Your makefile
Other Considerations
Porting from GCC* to the Intel® C++ Compiler
Overview: Porting from GCC* to the Intel® Compiler
Modifying Your makefile
Equivalent Macros
Other Considerations
Understanding the 64-bit Data Model used by OS X*
Compilation
Supported Environment Variables
Compilation Phases
Passing Options to the Linker
Linking Tools and Options
Specifying Alternate Tools and Paths
Using Configuration Files
Using Response Files
Global Symbols and Visibility Attributes
Specifying Symbol Visibility Explicitly
Saving Compiler Information in Your Executable
Linking Debug Information
Compiler Reference
C/C++ Calling Conventions
Compiler Options
Overview of Compiler Options
New Options
Deprecated and Removed Options
Displaying Alphabetical Lists of Compiler Options
Displaying Options Passed to Offload Compilation
Displaying Online Lists and Functional Groupings
Compiler Option Categories and Descriptions
Compiler Option Descriptions and General Rules
Offload Options
mmic, Qmic
offload, Qoffload
offload-attribute-target, Qoffload-attribute-target
offload-option, Qoffload-option
Optimization Options
falias
fast
fbuiltin, Oi
fdefer-pop
ffnalias
ffunction-sections
foptimize-sibling-calls
Gf
GF
nolib-inline
O
Oa
Od
Ofast
Os
Ot
Ow
Ox
Code Generation Options
arch
ax, Qax
EH
fasynchronous-unwind-tables
fexceptions
fomit-frame-pointer, Oy
Gd
Gr
GR
Gz
hotpatch
m
m32, m64
march
masm
minstruction, Qinstruction
mtune
Qcxx-features
Qpatchable-addresses
Qsafeseh
regcall, Qregcall
x, Qx
xHost, QxHost
Interprocedural Optimization (IPO) Options
ip, Qip
ip-no-inlining, Qip-no-inlining
ip-no-pinlining, Qip-no-pinlining
ipo, Qipo
ipo-c, Qipo-c
ipo-jobs, Qipo-jobs
ipo-S, Qipo-S
ipo-separate, Qipo-separate
Advanced Optimization Options
alias-const, Qalias-const
ansi-alias, Qansi-alias
ansi-alias-check, Qansi-alias-check
cilk-serialize, Qcilk-serialize
complex-limited-range, Qcomplex-limited-range
fargument-alias, Qalias-args
fargument-noalias-global
ffreestanding, Qfreestanding
fjump-tables
ftls-model
funroll-all-loops
guide, Qguide
guide-data-trans, Qguide-data-trans
guide-file, Qguide-file
guide-file-append, Qguide-file-append
guide-opts, Qguide-opts
guide-par, Qguide-par
guide-profile, Qguide-profile
guide-vec, Qguide-vec
ipp, Qipp
ipp-link, Qipp-link
mkl, Qmkl
opt-args-in-regs, Qopt-args-in-regs
opt-assume-safe-padding, Qopt-assume-safe-padding
opt-block-factor, Qopt-block-factor
opt-calloc, Qopt-calloc
opt-class-analysis, Qopt-class-analysis
opt-gather-scatter-unroll, Qopt-gather-scatter-unroll
opt-jump-tables, Qopt-jump-tables
opt-malloc-options
opt-matmul, Qopt-matmul
opt-mem-layout-trans, Qopt-mem-layout-trans
opt-multi-version-aggressive, Qopt-multi-version-aggressive
opt-prefetch, Qopt-prefetch
opt-prefetch-distance, Qopt-prefetch-distance
opt-ra-region-strategy, Qopt-ra-region-strategy
opt-streaming-cache-evict, Qopt-streaming-cache-evict
opt-streaming-stores, Qopt-streaming-stores
opt-subscript-in-range, Qopt-subscript-in-range
opt-threads-per-core, Qopt-threads-per-core
Qvla
scalar-rep, Qscalar-rep
simd, Qsimd
tbb, Qtbb
unroll, Qunroll
unroll-aggressive, Qunroll-aggressive
use-intel-optimized-headers, Quse-intel-optimized-headers
vec, Qvec
vec-guard-write, Qvec-guard-write
vec-threshold, Qvec-threshold
vecabi, Qvecabi
Profile Guided Optimization (PGO) Options
finstrument-functions, Qinstrument-functions
Gh
GH
p
prof-data-order, Qprof-data-order
prof-dir, Qprof-dir
prof-file, Qprof-file
prof-func-groups
prof-func-order, Qprof-func-order
prof-gen, Qprof-gen
prof-hotness-threshold, Qprof-hotness-threshold
prof-src-dir, Qprof-src-dir
prof-src-root, Qprof-src-root
prof-src-root-cwd, Qprof-src-root-cwd
prof-use, Qprof-use
prof-value-profiling, Qprof-value-profiling
profile-functions, Qprofile-functions
profile-loops, Qprofile-loops
profile-loops-report, Qprofile-loops-report
Qcov-dir
Qcov-file
Qcov-gen
Qfnsplit
Optimization Report Options
opt-report, Qopt-report
opt-report-file, Qopt-report-file
opt-report-help, Qopt-report-help
opt-report-phase, Qopt-report-phase
opt-report-routine, Qopt-report-routine
tcheck, Qtcheck
tcollect, Qtcollect
tcollect-filter, Qtcollect-filter
vec-report, Qvec-report
OpenMP* Options and Parallel Processing Options
fmpc-privatize
openmp, Qopenmp
openmp-lib, Qopenmp-lib
openmp-link, Qopenmp-link
openmp-offload, Qopenmp-offload
openmp-report, Qopenmp-report
openmp-simd, Qopenmp-simd
openmp-stubs, Qopenmp-stubs
openmp-task, Qopenmp-task
openmp-threadprivate, Qopenmp-threadprivate
par-affinity, Qpar-affinity
par-num-threads, Qpar-num-threads
par-report, Qpar-report
par-runtime-control, Qpar-runtime-control
par-schedule, Qpar-schedule
par-threshold, Qpar-threshold
parallel, Qparallel
parallel-source-info, Qparallel-source-info
Qpar-adjust-stack
Floating-Point Options
fast-transcendentals, Qfast-transcendentals
fimf-absolute-error, Qimf-absolute-error
fimf-accuracy-bits, Qimf-accuracy-bits
fimf-arch-consistency, Qimf-arch-consistency
fimf-domain-exclusion, Qimf-domain-exclusion
fimf-max-error, Qimf-max-error
fimf-precision, Qimf-precision
fma, Qfma
fp-model, fp
fp-port, Qfp-port
fp-speculation, Qfp-speculation
fp-stack-check, Qfp-stack-check
fp-trap, Qfp-trap
fp-trap-all, Qfp-trap-all
ftz, Qftz
Ge
mp1, Qprec
pc, Qpc
prec-div, Qprec-div
prec-sqrt, Qprec-sqrt
rcd, Qrcd
Inlining Options
fgnu89-inline
finline
finline-functions
finline-limit
inline-calloc, Qinline-calloc
inline-factor, Qinline-factor
inline-forceinline, Qinline-forceinline
inline-level, Ob
inline-max-per-compile, Qinline-max-per-compile
inline-max-per-routine, Qinline-max-per-routine
inline-max-size, Qinline-max-size
inline-max-total-size, Qinline-max-total-size
inline-min-size, Qinline-min-size
Qinline-dllimport
Output, Debug, and Precompiled Header (PCH) Options
c
debug (Linux* OS and OS* X)
debug (Windows* OS)
Fa
FA
fasm-blocks
FC
fcode-asm
Fd
FD
Fe
femit-class-debug-always
fmerge-constants
fmerge-debug-strings
Fo
Fp
Fr
FR
fsource-asm
ftrapuv, Qtrapuv
fverbose-asm
g, Zi, Z7
g0
gdwarf
Gm
grecord-gcc-switches
map-opts, Qmap-opts
o
pch
pch-create
pch-dir
pch-use
pdbfile
print-multi-lib
Qpchi
Quse-msasm-symbols
RTC
S
use-asm, Quse-asm
use-msasm
V
Y-
Yc
Yd
Yu
ZI
Preprocessor Options
A, QA
A-, QA-
B
C
D
dD, QdD
dM, QdM
dN, QdN
E
EP
FI
gcc, gcc-sys
H, QH
I
icc
idirafter
imacros
iprefix
iquote
isystem
iwithprefix
iwithprefixbefore
Kc++, TP
M, QM
MD, QMD
MF, QMF
MG, QMG
MM, QMM
MMD, QMMD
MP (Linux* OS)
MQ
MT, QMT
nostdinc++
P
pragma-optimization-level
u (Windows* OS)
U
undef
X
Component Control Options
Qinstall
Qlocation
Qoption
Language Options
ansi
check
check-uninit
early-template-check
fblocks
ffriend-injection
fno-gnu-keywords
fno-implicit-inline-templates
fno-implicit-templates
fno-operator-names
fno-rtti
fnon-lvalue-assign
fpermissive
fshort-enums
fsyntax-only
ftemplate-depth, Qtemplate-depth
funsigned-bitfields
funsigned-char
GZ
H (Windows* OS)
help-pragma, Qhelp-pragma
intel-extensions, Qintel-extensions
J
restrict, Qrestrict
std, Qstd
stdlib
strict-ansi
vd
vmb
vmg
vmm
vms
x (type option)
Za
Zc
Ze
Zg
Zp
Zs
Data Options
align
auto-ilp32, Qauto-ilp32
auto-p32
check-pointers, Qcheck-pointers
check-pointers-dangling, Qcheck-pointers-dangling
check-pointers-mpx, Qcheck-pointers-mpx
check-pointers-undimensioned, Qcheck-pointers-undimensioned
falign-functions
falign-stack
fcommon
fextend-arguments, Qextend-arguments
fkeep-static-consts, Qkeep-static-consts
fmath-errno
fminshared
fmudflap
fpack-struct
fpascal-strings
fpic
fpie
freg-struct-return
fstack-protector-all
fstack-security-check, GS
fvisibility
fvisibity-inlines-hidden
fzero-initialized-in-bss, Qzero-initialized-in-bss
GA
Gs
GT
homeparams
malign-double
malign-mac68k
malign-natural
malign-power
mcmodel
mdynamic-no-pic
mlong-double
mregparm
no-bss-init, Qnobss-init
noBool
Qlong-double
Qsfalign
Compiler Diagnostic Options
diag, Qdiag
diag-dump, Qdiag-dump
diag-enable sc, Qdiag-enable:sc
diag-enable sc-enums, Qdiag-enable:sc-enums
diag-enable sc-include, Qdiag-enable:sc-include
diag-enable sc-single-file, Qdiag-enable:sc-single-file
diag-error-limit, Qdiag-error-limit
diag-file, Qdiag-file
diag-file-append, Qdiag-file-append
diag-id-numbers, Qdiag-id-numbers
diag-once, Qdiag-once
diag-sc-dir, Qdiag-sc-dir
fnon-call-exceptions
traceback
w
w0...w5, W0...W5
Wabi
Wall
Wbrief
Wcheck
Wcomment
Wcontext-limit, Qcontext-limit
wd, Qwd
Wdeprecated
we, Qwe
Weffc++, Qeffc++
Werror, WX
Werror-all
Wextra-tokens
Wformat
Wformat-security
Wic-pointer
Winline
WL
Wmain
Wmissing-declarations
Wmissing-prototypes
wn, Qwn
Wnon-virtual-dtor
wo, Qwo
Wp64
Wpch-messages
Wpointer-arith
Wport
Wpragma-once
wr, Qwr
Wremarks
Wreorder
Wreturn-type
Wshadow
Wsign-compare
Wstrict-aliasing
Wstrict-prototypes
Wtrigraphs
Wuninitialized
Wunknown-pragmas
Wunused-function
Wunused-variable
ww, Qww
Wwrite-strings
Compatibility Options
clang-name
clangxx-name
fabi-version
fms-dialect
gcc-name
gnu-prefix
gxx-name
Qgcc-dialect
Qms
Qvc
use-clang-env
vmv
Linking or Linker Options
Bdynamic
Bstatic
Bsymbolic
Bsymbolic-functions
cxxlib
dynamic-linker
dynamiclib
F (Windows* OS)
F (OS* X)
fixed
Fm
l
L
LD
link
MD
MT
no-libgcc
nodefaultlibs
nostartfiles
nostdlib
pie
pthread
shared
shared-intel
shared-libgcc
static
static-intel
static-libgcc
static-libstdc++
staticlib
T
u (Linux* OS)
v
Wa
Wl
Wp
Xlinker
Zl
Miscellaneous Options
bigobj
dryrun
dumpmachine
dumpversion
global-hoist, Qglobal-hoist
Gy
help
multibyte-chars, Qmultibyte-chars
multiple-processes, MP
nologo
save-temps, Qsave-temps
showIncludes
sox
sysroot
Tc
TC
Tp
V, QV
version
watch
Alternate Compiler Options
Related Options
Portability Options
GCC-Compatible Warning Options
Floating-point Operations
Understanding Floating-point Operations
Programming Tradeoffs in Floating-point Applications
Floating-point Optimizations
Using the -fp-model (/fp) Option
Denormal Numbers
Floating-point Environment
Setting the FTZ and DAZ Flags
Checking the Floating-point Stack State
Tuning Performance
Overview: Tuning Performance
Handling Floating-point Array Operations in a Loop Body
Reducing the Impact of Denormal Exceptions
Avoiding Mixed Data Type Arithmetic Expressions
Using Efficient Data Types
Understanding IEEE Floating-point Operations
Overview: Understanding IEEE Floating-point Standard
Floating-point Formats
Special Values
Intel® IEEE 754-2008 Binary Floating-Point Conformance Library
Overview: Intel® IEEE 754-2008 Binary Floating-point Conformance Library
Using the Intel® IEEE 754-2008 Binary Floating-point Conformance Library
Function List
Homogeneous General-Computational Operations Functions
General-Computational Operations Functions
Quiet-Computational Operations Functions
Signaling-Computational Operations Functions
Non-Computational Operations Functions
Intel® Numeric String Conversion Library
Overview
Function List
Attributes
align
align_value
avoid_false_share
concurrency_safe
const
cpu_dispatch
cpu_specific
target
vector
Intrinsics
Overview
Overview: Intrinsics Reference
Details about Intrinsics
Naming and Usage Syntax
Links and Bibliography
Intrinsics for All Intel Architectures
Overview: Intrinsics across Intel® Architectures
Integer Arithmetic Intrinsics
Floating-point Intrinsics
String and Block Copy Intrinsics
Miscellaneous Intrinsics
_may_i_use_cpu_feature
_allow_cpu_features
Data Alignment, Memory Allocation Intrinsics, and Inline Assembly
Overview
Alignment Support
Allocating and Freeing Aligned Memory Blocks
Inline Assembly
Intrinsics for Managing Extended Processor States and Registers
Overview
Intrinsics for Reading and Writing the Content of Extended Control Registers
_xgetbv()
_xsetbv()
Intrinsics for Saving and Restoring the Extended Processor States
_fxsave()
_fxsave64()
_fxrstor()
_fxrstor64()
_xsave()
_xsave64()
_xsaveopt()
_xsaveopt64()
_xrstor()
_xrstor64()
Intrinsics for Intel® MIC Architecture
Overview: Intrinsics Supporting Intel® Initial Many Core Instructions (Intel® IMCI)
Details of Intrinsic Functions for Intel® Many Integrated Core Architecture (Intel® MIC Architecture)
Details about Intrinsic Functions Supporting Intel® Initial Many Core Instructions (Intel® IMCI)
Data Types for Intel® Many Integrated Core Architecture (Intel® MIC Architecture)
Shuffle Intrinsics
_mm512_swizzle_ps/ _mm512_mask_swizzle_ps
_mm512_swizzle_epi32/ _mm512_mask_swizzle_epi32
_mm512_swizzle_pd/ _mm512_mask_swizzle_pd
_mm512_swizzle_epi64/ _mm512_mask_swizzle_epi64
_mm512_shuffle_epi32/ _mm512_mask_shuffle_epi32
_mm512_permute4f128_epi32/ _mm512_mask_permute4f128_epi32
_mm512_permutevar_epi32/ _mm512_mask_permutevar_epi32
Vector Intrinsics
Overview: Vector Operations
Arithmetic Intrinsics
Addition Operations
_mm512_add_epi32/ _mm512_mask_add_epi32
_mm512_add_epi64/ _mm512_mask_add_epi64
_mm512_add_ps/ _mm512_mask_add_ps
_mm512_add_pd/ _mm512_mask_add_pd
_mm512_addn_ps/ _mm512_mask_addn_ps
_mm512_addn_pd/ _mm512_mask_addn_pd
_mm512_addsets_epi32/ _mm512_mask_addsets_epi32
_mm512_addsets_ps/ _mm512_mask_addsets_ps
_mm512_addsetc_epi32/ _mm512_mask_addsetc_epi32
_mm512_adc_epi32/ _mm512_mask_adc_epi32
_mm512_addn_round_pd/ _mm512_mask_addn_round_pd
_mm512_addn_round_ps/ _mm512_mask_addn_round_ps
_mm512_add_round_pd/ _mm512_mask_add_round_pd
_mm512_add_round_ps/ _mm512_mask_add_round_ps
_mm512_addsets_round_ps/ _mm512_mask_addsets_round_ps
Multiplication Operations
_mm512_fmadd[_round]_ps/ _mm512_mask[3]_fmadd[_round]_ps
_mm512_fmadd[_round]_pd/ _mm512_mask[3]_fmadd[_round]_pd
_mm512_fmadd_epi32/ _mm512_mask[3]_fmadd_epi32
_mm512_fmadd233_epi32/ _mm512_mask_fmadd233_epi32
_mm512_fmadd233[_round]_ps/ _mm512_mask_fmadd233[_round]_ps
_mm512_fnmadd[_round]_ps/ _mm512_mask[3]_fnmadd[_round]_ps
_mm512_fnmadd[_round]_pd/ _mm512_mask[3]_fnmadd[_round]_pd
_mm512_fmsub[_round]_ps/ _mm512_mask[3]_fmsub[_round]_ps
_mm512_fmsub[_round]_pd/ _mm512_mask[3]_fmsub[_round]_pd
_mm512_fnmsub[_round]_ps/ _mm512_mask[3]_fnmsub[_round]_ps
_mm512_fnmsub[_round]_pd/ _mm512_mask[3]_fnmsub[_round]_pd
_mm512_mulhi_epi32/ _mm512_mask_mulhi_epi32
_mm512_mulhi_epu32/ _mm512_mask_mulhi_epu32
_mm512_mullo_epi32/ _mm512_mask_mullo_epi32
_mm512_mul_pd/ _mm512_mask_mul_pd
_mm512_mul_ps/ _mm512_mask_mul_ps
_mm512_mul_round_pd/ _mm512_mask_mul_round_pd
_mm512_mul_round_ps/ _mm512_mask_mul_round_ps
_mm512_scale_ps/ _mm512_mask_scale_ps
_mm512_scale_round_ps/ _mm512_mask_scale_round_ps
Subtraction Operations
_mm512_sub_epi32/ _mm512_mask_sub_epi32
_mm512_sub_ps/ _mm512_mask_sub_ps
_mm512_sub_pd/ _mm512_mask_sub_pd
_mm512_subr_epi32/ _mm512_mask_subr_epi32
_mm512_subr_pd/ _mm512_mask_subr_pd
_mm512_subr_ps/ _mm512_mask_subr_ps
_mm512_sbbr_epi32/ _mm512_mask_sbbr_epi32
_mm512_subsetb_epi32/ _mm512_mask_subsetb_epi32
_mm512_subrsetb_epi32/ _mm512_mask_subrsetb_epi32
_mm512_sbb_epi32/ _m512_mask_sbb_epi32
_mm512_sub_round_pd/ _mm512_mask_sub_round_pd
_mm512_sub_round_ps/ _mm512_mask_sub_round_ps
_mm512_subr_round_pd/ _mm512_mask_subr_round_pd
_mm512_subr_round_ps/ _mm512_mask_subr_round_ps
Bitwise Intrinsics
_mm512_and_epi32/ _mm512_mask_and_epi32
_mm512_and_epi64/ _mm512_mask_and_epi64
_mm512_andnot_epi32/ _mm512_mask_andnot_epi32
_mm512_andnot_epi64/ _mm512_mask_andnot_epi64
_mm512_or_epi32/ _mm512_mask_or_epi32
_mm512_or_epi64/ _mm512_mask_or_epi64
_mm512_test_epi32_mask/ _mm512_mask_test_epi32_mask
_mm512_xor_epi32/ _mm512_mask_xor_epi32
_mm512_xor_epi64/ _mm512_mask_xor_epi64
Compare Intrinsics
Compare Operations between Floating Point Vectors
Compare Instructions for Floating Point Vectors
_mm512_cmp_pd_mask/ _mm512_mask_cmp_pd_mask
_mm512_cmp_ps_mask/ _mm512_mask_cmp_ps_mask
Compare Operations between Integer Vectors
_mm512_cmp_epi32_mask/ _mm512_mask_cmp_epi32_mask
_mm512_cmp_epu32_mask/ _mm512_mask_cmp_epu32_mask
Conversion Intrinsics
_mm512_cvtpd_pslo/ _mm512_mask_cvtpd_pslo
_mm512_cvt_roundpd_pslo/ _mm512_mask_cvt_roundpd_pslo
_mm512_cvtfxpnt_roundpd_epi32lo/ _mm512_mask_cvtfxpnt_roundpd_epi32lo
_mm512_cvtfxpnt_roundpd_epu32lo/ _mm512_mask_cvtfxpnt_roundpd_epu32lo
_mm512_cvtpslo_pd/ _mm512_mask_cvtpslo_pd
_mm512_cvtepu32lo_pd/ _mm512_mask_cvtepu32lo_pd
_mm512_cvtepi32lo_pd/ _mm512_mask_cvtepi32lo_pd
_mm512_cvtfxpnt_round_adjustepu32_ps/ _mm512_mask_cvtfxpnt_round_adjustepu32_ps
_mm512_cvtfxpnt_round_adjustps_epi32/ _mm512_mask_cvtfxpnt_round_adjustps_epi32
_mm512_cvtfxpnt_round_adjustps_epu32/ _mm512_mask_cvtfxpnt_round_adjustps_epu32
_mm512_cvtfxpnt_round_adjustepu32_ps/ _mm512_mask_cvtfxpnt_round_adjustepu32_ps
_mm512_round_ps/ _mm512_mask_round_ps
Load Intrinsics
_mm512_extload_ps/ _mm512_mask_extload_ps
_mm512_load_ps/ _mm512_mask_load_ps
_mm512_extload_epi32/ _mm512_mask_extload_epi32
_mm512_load_epi32/ _mm512_mask_load_epi32
_mm512_extload_pd/ _mm512_mask_extload_pd
_mm512_load_pd/ _mm512_mask_load_pd
_mm512_extload_epi64/ _mm512_mask_extload_epi64
_mm512_load_epi64/ _mm512_mask_load_epi64
_mm512_loadunpackhi_epi32/ _mm512_mask_loadunpackhi_epi32
_mm512_extloadunpackhi_epi32/ _mm512_mask_extloadunpackhi_epi32
_mm512_loadunpacklo_epi32/ _mm512_mask_loadunpacklo_epi32
_mm512_extloadunpacklo_epi32/ _mm512_mask_extloadunpacklo_epi32
_mm512_loadunpackhi_epi64/ _mm512_mask_loadunpackhi_epi64
_mm512_extloadunpackhi_epi64/ _mm512_mask_extloadunpackhi_epi64
_mm512_loadunpacklo_epi64/ _mm512_mask_loadunpacklo_epi64
_mm512_extloadunpacklo_epi64/ _mm512_mask_extloadunpacklo_epi64
_mm512_loadunpackhi_ps/ _mm512_mask_loadunpackhi_ps
_mm512_extloadunpackhi_ps/ _mm512_mask_extloadunpackhi_ps
_mm512_loadunpacklo_ps/ _mm512_mask_loadunpacklo_ps
_mm512_extloadunpacklo_ps/ _mm512_mask_extloadunpacklo_ps
_mm512_loadunpackhi_pd/ _mm512_mask_loadunpackhi_pd
_mm512_extloadunpackhi_pd/ _mm512_mask_extloadunpackhi_pd
_mm512_loadunpacklo_pd/ _mm512_mask_loadunpacklo_pd
_mm512_extloadunpacklo_pd/ _mm512_mask_extloadunpacklo_pd
Gather and Scatter Intrinsics
_mm512_i32[ext]gather_ps/ _mm512_mask_i32[ext]gather_ps
_mm512_i32[ext]gather_epi32/ _mm512_mask_i32[ext]gather_epi32
_mm512_i32lo[ext]gather_pd/ _mm512_mask_i32lo[ext]gather_pd
_mm512_i32lo[ext]gather_epi64/ _mm512_mask_i32lo[ext]gather_epi64
_mm512_prefetch_i32[ext]gather_ps/ _mm512_mask_prefetch_i32[ext]gather_ps
_mm512_i32[ext]scatter_ps/ _mm512_mask_i32[ext]scatter_ps
_mm512_i32[ext]scatter_epi32/ _mm512_mask_i32[ext]scatter_epi32
_mm512_i32lo[ext]scatter_pd/ _mm512_mask_i32lo[ext]scatter_pd
_mm512_i32lo[ext]scatter_epi64/ _mm512_mask_i32lo[ext]scatter_epi64
_mm512_prefetch_i32[ext]scatter_ps/ _mm512_mask_prefetch_i32[ext]scatter_ps
Intrinsics to Determine Maximum and Minimum Values
_mm512_[g]maxabs_ps/ _mm512_mask_[g]maxabs_ps
_mm512_gmax_pd/ _mm512_mask_gmax_pd
_mm512_max_pd/ _mm512_mask_max_pd
_mm512_gmax_ps/ _mm512_mask_gmax_ps
_mm512_max_ps/ _mm512_mask_max_ps
_mm512_max_epi32/ _mm512_mask_max_epi32
_mm512_max_epu32/ _mm512_mask_max_epu32
_mm512_gmin_pd/ _mm512_mask_gmin_pd
_mm512_min_pd/ _mm512_mask_min_pd
_mm512_gmin_ps/ _mm512_mask_gmin_ps
_mm512_min_ps/ _mm512_mask_min_ps
_mm512_min_epi32/ _mm512_mask_min_epi32
_mm512_min_epu32/ _mm512_mask_min_epu32
Miscellaneous Intrinsics
_mm512_alignr_epi32/ _mm512_mask_alignr_epi32
_mm512_exp223_ps/ _mm512_mask_exp223_ps
_mm512_fixupnan_pd/ _mm512_mask_fixupnan_pd
_mm512_fixupnan_ps/ _mm512_mask_fixupnan_ps
_mm512_getexp_ps/ _mm512_mask_getexp_ps
_mm512_getexp_pd/ _mm512_mask_getexp_pd
_mm512_getmant_pd/ _mm512_mask_getmant_pd
_mm512_getmant_ps/ _mm512_mask_getmant_ps
_mm512_log2ae23_ps/ _mm512_mask_log2ae23_ps
_mm512_rcp23_ps/ _mm512_mask_rcp23_ps
_mm512_roundfxpnt_adjust_ps/ _mm512_mask_roundfxpnt_adjust_ps
_mm512_roundfxpnt_adjust_pd/ _mm512_mask_roundfxpnt_adjust_pd
_mm512_rsqrt23_ps/ _mm512_mask_rsqrt23_ps
Memory and Initialization Intrinsics
_mm512_setzero_pd/ _mm512_setzero_ps/ _mm512_setzero_epi32
_mm512_setr_pd
_mm512_setr_ps
_mm512_set1_pd
_mm512_set1_epi64
_mm512_set1_ps
_mm512_set1_epi32
_mm512_set[r]4_pd
_mm512_set[r]4_epi64
_mm512_set[r]4_ps
_mm512_set[r]4_epi32
_mm512_set_ps
_mm512_set_epi32
_mm512_set_pd
_mm512_set[r]_epi64
_mm512_mask_mov_ps/ _mm512_mask_mov_epi32
_mm512_mask_mov_pd/ _mm512_mask_mov_epi64
_mm512_undefined_ps/ _mm512_undefined_pd/ _mm512_undefined_epi32
Shift Intrinsics
_mm512_sllv_epi32/ _mm512_mask_sllv_epi32
_mm512_srav_epi32/ _mm512_mask_srav_epi32
_mm512_srlv_epi32/ _mm512_mask_srlv_epi32
_mm512_slli_epi32/ _mm512_mask_slli_epi32
_mm512_srai_epi32/ _mm512_mask_srai_epi32
_mm512_srli_epi32/ _mm512_mask_srli_epi32
Store Intrinsics
_mm512_store_ps/ _mm512_mask_store_ps
_mm512_extstore_ps/ _mm512_mask_extstore_ps
_mm512_store_epi32/ _mm512_mask_store_epi32
_mm512_extstore_epi32/ _mm512_mask_extstore_epi32
_mm512_store_pd/ _mm512_mask_store_pd
_mm512_extstore_pd/ _mm512_mask_extstore_pd
_mm512_store_epi64/ _mm512_mask_store_epi64
_mm512_extstore_epi64/ _mm512_mask_extstore_epi64
_mm512_packstorehi_epi32/ _mm512_mask_packstorehi_epi32
_mm512_extpackstorehi_epi32/ _mm512_mask_extpackstorehi_epi32
_mm512_packstorelo_epi32/ _mm512_mask_packstorelo_epi32
_mm512_extpackstorelo_epi32/ _mm512_mask_extpackstorelo_epi32
_mm512_packstorehi_epi64/ _mm512_mask_packstorehi_epi64
_mm512_extpackstorehi_epi64/ _mm512_mask_extpackstorehi_epi64
_mm512_packstorelo_epi64/ _mm512_mask_packstorelo_epi64
_mm512_extpackstorelo_epi64/ _mm512_mask_extpackstorelo_epi64
_mm512_packstorehi_ps/ _mm512_mask_packstorehi_ps
_mm512_extpackstorehi_ps/ _mm512_mask_extpackstorehi_ps
_mm512_packstorelo_ps/ _mm512_mask_packstorelo_ps
_mm512_extpackstorelo_ps/ _mm512_mask_extpackstorelo_ps
_mm512_packstorehi_pd/ _mm512_mask_packstorehi_pd
_mm512_extpackstorehi_pd/ _mm512_mask_extpackstorehi_pd
_mm512_packstorelo_pd/ _mm512_mask_packstorelo_pd
_mm512_extpackstorelo_pd/ _mm512_mask_extpackstorelo_pd
_mm512_storenr_ps
_mm512_storenr_pd
_mm512_storenrngo_ps
_mm512_storenrngo_pd
Short Vector Math Library Intrinsics
Overview: SVML Intrinsics
Division Operations
_mm512_div_pd/ _mm512_mask_div_pd
_mm512_div_ps/ _mm512_mask_div_ps
_mm512_div_epi8
_mm512_div_epi16
_mm512_div_epi32/ _mm512_mask_div_epi32
_mm512_div_epi64
_mm512_div_epu8
_mm512_div_epu16
_mm512_div_epu32/ _mm512_mask_div_epu32
_mm512_div_epu64
_mm512_rem_epi8
_mm512_rem_epi16
_mm512_rem_epi32/ _mm512_mask_rem_epi32
_mm512_rem_epi64
_mm512_rem_epu8
_mm512_rem_epu32/ _mm512_mask_rem_epu32
_mm512_rem_epu16
_mm512_mm512_rem_epu64
Error Function Operations
_mm512_cdfnorminv_pd/ _mm512_mask_cdfnorminv_pd
_mm512_cdfnorminv_ps/ _mm512_mask_cdfnorminv_ps
_mm512_erf_pd/ _mm512_mask_erf_pd
_mm512_erf_ps/ _mm512_mask_erf_ps
_mm512_erfc_pd/ _mm512_mask_erfc_pd
_mm512_erfc_ps/ _mm512_mask_erfc_ps
_mm512_erfinv_pd/ _mm512_mask_erfinv_pd
_mm512_erfinv_ps/ _mm512_mask_erfinv_ps
Exponential Operations
_mm512_exp10_pd/ _mm512_mask_exp10_pd
_mm512_exp10_ps/ _mm512_mask_exp10_ps
_mm512_exp2_pd/ _mm512_mask_exp2_pd
_mm512_exp2_ps/ _mm512_mask_exp2_ps
_mm512_exp_pd/ _mm512_mask_exp_pd
_mm512_exp_ps/ _mm512_mask_exp_ps
_mm512_expm1_pd/ _mm512_mask_expm1_pd
_mm512_expm1_ps/ _mm512_mask_expm1_ps
_mm512_pow_pd/ _mm512_mask_pow_pd
_mm512_pow_ps/ _mm512_mask_pow_ps
Logarithmic Operations
_mm512_log10_pd/ _mm512_mask_log10_pd
_mm512_log10_ps/ _mm512_mask_log10_ps
_mm512_log2_pd/ _mm512_mask_log2_pd
_mm512_log2_ps/ _mm512_mask_log2_ps
_mm512_log_pd/ _mm512_mask_log_pd
_mm512_log_ps/ _mm512_mask_log_ps
_mm512_logb_pd/ _mm512_mask_logb_pd
_mm512_logb_ps/ _mm512_mask_logb_ps
_mm512_log1p_pd/ _mm512_mask_log1p_pd
_mm512_log1p_ps/ _mm512_mask_log1p_ps
Rounding Off Operations
_mm512_ceil_pd/ _mm512_mask_ceil_pd
_mm512_ceil_ps/ _mm512_mask_ceil_ps
_mm512_floor_pd/ _mm512_mask_floor_pd
_mm512_floor_ps/ _mm512_mask_floor_ps
_mm512_nearbyint_pd/ _mm512_mask_nearbyint_pd
_mm512_nearbyint_ps/ _mm512_mask_nearbyint_ps
_mm512_rint_pd/ _mm512_mask_rint_pd
_mm512_rint_ps/ _mm512_mask_rint_ps
_mm512_svml_round_pd/ _mm512_mask_svml_round_pd
_mm512_trunc_pd/ _mm512_mask_trunc_pd
_mm512_trunc_ps/ _mm512_mask_trunc_ps
Square Root and Cube Root Operations
_mm512_sqrt_pd/ _mm512_mask_sqrt_pd
_mm512_sqrt_ps/ _mm512_mask_sqrt_ps
_mm512_invsqrt_pd/ _mm512_mask_invsqrt_pd
_mm512_invsqrt_ps/ _mm512_mask_invsqrt_ps
_mm512_hypot_pd/ _mm512_mask_hypot_pd
_mm512_hypot_ps/ _mm512_mask_hypot_ps
_mm512_cbrt_pd/ _mm512_mask_cbrt_pd
_mm512_cbrt_ps/ _mm512_mask_cbrt_ps
Trigonometric Operations
_mm512_cos_pd/ _mm512_mask_cos_pd
_mm512_cos_ps/ _mm512_mask_cos_ps
_mm512_cosd_pd/ _mm512_mask_cosd_pd
_mm512_cosd_ps/ _mm512_mask_cosd_ps
_mm512_cosh_pd/ _mm512_mask_cosh_pd
_mm512_cosh_ps/ _mm512_mask_cosh_ps
_mm512_acos_pd/ _mm512_mask_acos_pd
_mm512_acos_ps/ _mm512_mask_acos_ps
_mm512_acosh_pd/ _mm512_mask_acosh_pd
_mm512_acosh_ps/ _mm512_mask_acosh_ps
_mm512_sin_pd/ _mm512_mask_sin_pd
_mm512_sin_ps/ _mm512_mask_sin_ps
_mm512_sind_pd/ _mm512_mask_sind_pd
_mm512_sind_ps/ _mm512_mask_sind_ps
_mm512_sinh_pd/ _mm512_mask_sinh_pd
_mm512_sinh_ps/ _mm512_mask_sinh_ps
_mm512_asin_pd/ _mm512_mask_asin_pd
_mm512_asin_ps/ _mm512_mask_asin_ps
_mm512_asinh_pd/ _mm512_mask_asinh_pd
_mm512_asinh_ps/ _mm512_mask_asinh_ps
_mm512_tan_pd/ _mm512_mask_tan_pd
_mm512_tan_ps/ _mm512_mask_tan_ps
_mm512_tand_pd/ _mm512_mask_tand_pd
_mm512_tand_ps/ _mm512_mask_tand_ps
_mm512_tanh_pd/ _mm512_mask_tanh_pd
_mm512_tanh_ps/ _mm512_mask_tanh_ps
_mm512_atan_pd/ _mm512_mask_atan_pd
_mm512_atan_ps/ _mm512_mask_atan_ps
_mm512_atanh_pd/ _mm512_mask_atanh_pd
_mm512_atanh_ps/ _mm512_mask_atanh_ps
_mm512_atan2_pd/ _mm512_mask_atan2_pd
_mm512_atan2_ps/ _mm512_mask_atan2_ps
Type Cast Intrinsics
Using Type Cast Intrinsics
_mm512_castpd_ps
_mm512_castps_pd
_mm512_castps_si512
_mm512_castsi512_ps
_mm512_castpd_si512
_mm512_castsi512_pd
Vector Mask Intrinsics
_mm512_kand
_mm512_kandn
_mm512_kandnr
_mm512_movlhb
_mm512_kmov
_mm512_knot
_mm512_kor
_mm512_kxnor
_mm512_kxor
_mm512_kswapb
_mm512_kortestz
_mm512_kortestc
_mm512_mask2int
_mm512_int2mask
_mm512_kconcathi_64
_mm512_kconcatlo_64
_mm512_kextract_64
Intrinsics for Blend Operations
_mm512_mask_blend_epi32
_mm512_mask_blend_epi64
_mm512_mask_blend_pd
_mm512_mask_blend_ps
Reduction Intrinsics
Overview: Reduction Intrinsics
_mm512_reduce_add_ps/ _mm512_mask_reduce_add_ps
_mm512_reduce_add_pd/ _mm512_mask_reduce_add_pd
_mm512_reduce_add_epi32/ _mm512_mask_reduce_add_epi32
_mm512_reduce_and_epi32/ _mm512_mask_reduce_and_epi32
_mm512_reduce_or_epi32/ _mm512_mask_reduce_or_epi32
_mm512_reduce_[g]max_ps/ _mm512_mask_reduce_[g]max_ps
_mm512_reduce_[g]max_pd/ _mm512_mask_reduce_[g]max_pd
_mm512_reduce_max_epi32/ _mm512_mask_reduce_max_epi32
_mm512_reduce_max_epu32/ _mm512_mask_reduce_max_epu32
_mm512_reduce_[g]min_ps/ _mm512_mask_reduce_[g]min_ps
_mm512_reduce_[g]min_pd/ _mm512_mask_reduce_[g]min_pd
_mm512_reduce_min_epi32/ _mm512_mask_reduce_min_epi32
_mm512_reduce_min_epu32/ _mm512_mask_reduce_min_epu32
_mm512_reduce_mul_ps/ _mm512_mask_reduce_mul_ps
_mm512_reduce_mul_pd/ _mm512_mask_reduce_mul_pd
_mm512_reduce_mul_epi32/ _mm512_mask_reduce_mul_epi32
Scalar Intrinsics
Overview: Scalar Intrinsics
_mm_countbits
_mm_delay
_mm_spflt
_mm_tzcnt
_mm_tzcnti
_mm_clevict
Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Instructions
Overview: Intrinsics for Intel® Advanced Vector Extensions 512 (Intel® AVX-512) Instructions
Intrinsics for Arithmetic Operations
Intrinsics for Addition Operations
Intrinsics for FP Addition Operations
Intrinsics for Integer Addition Operations
Intrinsics for Determining Minimum and Maximum Values
Intrinsics for Determining Minimum and Maximum FP Values
Intrinsics for Determining Minimum and Maximum Integer Values
Intrinsics for FP Fused Multiply-Add (FMA) Operations
Intrinsics for Multiplication Operations
Intrinsics for FP Multiplication Operations
Intrinsics for Integer Multiplication Operations
Intrinsics for Subtraction Operations
Intrinsics for FP Subtraction Operations
Intrinsics for Integer Subtraction Operations
Intrinsics for Short Vector Math Library (SVML) Operations
Intrinsics for Division Operations
Intrinsics for Error Function Operations
Intrinsics for Exponential Operations
Intrinsics for Logarithmic Operations
Intrinsics for Reciprocal Operations
Intrinsics for Root Function Operations
Intrinsics for Rounding Operations
Intrinsics for Trigonometric Operations
Intrinsics for Other Mathematics Operations
Intrinsics for FP Division Operations
Intrinsics for Absolute Value Operations
Intrinsics for Scale Operations
Intrinsics for Blend Operations
Intrinsics for Integer Bit Manipulation Operations
Intrinsics for Bit Manipulation and Conflict Detection Operations
Intrinsics for Bitwise Logical Operations
Intrinsics for Integer Bit Rotation Operations
Intrinsics for Integer Bit Shift Operations
Intrinsics for Broadcast Operations
Intrinsics for FP Broadcast Operations
Intrinsics for Integer Broadcast Operations
Intrinsics for Comparison Operations
Intrinsics for FP Comparison Operations
Intrinsics for Integer Comparison Operations
Intrinsics for Compression Operations
Intrinsics for Conversion Operations
Intrinsics for FP Conversion Operations
Intrinsics for Integer Conversion Operations
Intrinsics for Expand and Load Operations
Intrinsics for FP Expand and Load Operations
Intrinsics for Integer Expand and Load Operations
Intrinsics for Gather and Scatter Operations
Intrinsics for FP Gather and Scatter Operations
Intrinsics for Integer Gather and Scatter Operations
Intrinsics for Insert and Extract Operations
Intrinsics for FP Insert and Extract Operations
Intrinsics for Integer Insert and Extract Operations
Intrinsics for Load and Store Operations
Intrinsics for FP Load and Store Operations
Intrinsics for Integer Load and Store Operations
Intrinsics for Miscellaneous Operations
Intrinsics for Miscellaneous FP Operations
Intrinsics for Miscellaneous Integer Operations
Intrinsics for Move Operations
Intrinsics for FP Move Operations
Intrinsics for Integer Move Operations
Intrinsics for Pack and Unpack Operations
Intrinsics for FP Pack and Store Operations
Intrinsics for Integer Pack and Unpack Operations
Intrinsics for Permutation Operations
Intrinsics for FP Permutation Operations
Intrinsics for Integer Permutation Operations
Intrinsics for Reduction Operations
Intrinsics for FP Reduction Operations
Intrinsics for Reduction Operations
Intrinsics for Set Operations
Intrinsics for Shuffle Operations
Intrinsics for FP Shuffle Operations
Intrinsics for Integer Shuffle Operations
Intrinsics for Test Operations
Intrinsics for Typecast Operations
Intrinsics for Vector Mask Operations
Intrinsics for Later Generation Intel® Core™ Processor Instruction Extensions
Overview: Intrinsics for 3rd Generation Intel® Core™ Processor Instruction Extensions
Overview: Intrinsics for 4th Generation Intel® Core™ Processor Instruction Extensions
Intrinsics for Converting Half Floats that Map to 3rd Generation Intel® Core™ Processor Instructions
_mm_cvtph_ps()
_mm256_cvtph_ps()
_mm_cvtps_ph()
_mm256_cvtps_ph()
Intrinsics that Generate Random Numbers of 16/32/64 Bit Wide Random Integers
_rdrand_u16(), _rdrand_u32(), _rdrand_u64()
_rdseed_u16(), _rdseed_u32(), _rdseed_u64()
Intrinsics for Multi-Precision Arithmetic
_addcarry_u32(), _addcarry_u64()
_addcarryx_u32(), _addcarryx_u64()
_subborrow_u32(), _subborrow_u64()
Intrinsics that Allow Reading from and Writing to the FS Base and GS Base Registers
_readfsbase_u32(), _readfsbase_u64()
_readgsbase_u32(), _readgsbase_u64()
_writefsbase_u32(), _writefsbase_u64()
_writegsbase_u32(), _writegsbase_u64()
Intrinsics for Intel® Advanced Vector Extensions 2
Overview: Intrinsics for Intel® Advanced Vector Extensions 2 Instructions
Intrinsics for Arithmetic Operations
_mm256_abs_epi8/16/32
_mm256_add_epi8/16/32/64
_mm256_adds_epi8/16
_mm256_adds_epu8/16
_mm256_sub_epi8/16/32/64
_mm256_subs_epi8/16
_mm256_subs_epu8/16
_mm256_avg_epu8/16
_mm256_hadd_epi16/32
_mm256_hadds_epi16
_mm256_hsub_epi16/32
_mm256_hsubs_epi16
_mm256_madd_epi16
_mm256_maddubs_epi16
_mm256_mul_epi32
_mm256_mul_epu32
_mm256_mulhi_epi16
_mm256_mulhi_epu16
_mm256_mullo_epi16/32
_mm256_mulhrs_epi16
_mm256_sign_epi8/16/32
_mm256_mpsadbw_epu8
_mm256_sad_epu8
Intrinsics for Arithmetic Shift Operations
_mm256_sra_epi16/32
_mm256_srai_epi16/32
_mm256_srav_epi32
_mm_srav_epi32
Intrinsics for Blend Operations
_mm_blend_epi32/ _mm256_blend_epi16/32
_mm256_blendv_epi8
Intrinsics for Bitwise Operations
_mm256_and_si256
_mm256_andnot_si256
_mm256_or_si256
_mm256_xor_si256
Intrinsics for Broadcast Operations
_mm_broadcastss_ps/ _mm256_broadcastss_ps
_mm_broadcastsd_pd/ _mm256_broadcastsd_pd
_mm_broadcastb_epi8/ _mm256_broadcastb_epi8
_mm_broadcastw_epi16/ _mm256_broadcastw_epi16
_mm_broadcastd_epi32/ _mm256_broadcastd_epi32
_mm_broadcastq_epi64/ _mm256_broadcastq_epi64
_mm256_broadcastsi128_si256
Intrinsics for Compare Operations
_mm256_cmpeq_epi8/16/32/64
_mm256_cmpgt_epi8/16/32/64
_mm256_max_epi8/16/32
_mm256_max_epu8/16/32
_mm256_min_epi8/16/32
_mm256_min_epu8/16/32
Intrinsics for Fused Multiply Add Operations
_mm_fmadd_pd/ _mm256_fmadd_pd
_mm_fmadd_ps/ _mm256_fmadd_ps
_mm_fmadd_sd
_mm_fmadd_ss
_mm_fmaddsub_pd/ _mm256_fmaddsub_pd
_mm_fmaddsub_ps/ _mm256_fmaddsub_ps
_mm_fmsub_pd/ _mm256_fmsub_pd
_mm_fmsub_ps/ _mm256_fmsub_ps
_mm_fmsub_sd
_mm_fmsub_ss
_mm_fmsubadd_pd/ _mm256_fmsubadd_pd
_mm_fmsubadd_ps/ _mm256_fmsubadd_ps
_mm_fnmadd_pd/ _mm256_fnmadd_pd
_mm_fnmadd_ps/ _mm256_fnmadd_ps
_mm_fnmadd_sd
_mm_fnmadd_ss
_mm_fnmsub_pd/ _mm256_fnmsub_pd
_mm_fnmsub_ps/ _mm256_fnmsub_ps
_mm_fnmsub_sd
_mm_fnmsub_ss
Intrinsics for GATHER Operations
_mm_mask_i32gather_pd/ _mm256_mask_i32gather_pd
_mm_i32gather_pd/ _mm256_i32gather_pd
_mm_mask_i64gather_pd/ _mm256_mask_i64gather_pd
_mm_i64gather_pd/ _mm256_i64gather_pd
_mm_mask_i32gather_ps/ _mm256_mask_i32gather_ps
_mm_i32gather_ps/ _mm256_i32gather_ps
_mm_mask_i64gather_ps/ _mm256_mask_i64gather_ps
_mm_i64gather_ps/ _mm256_i64gather_ps
_mm_mask_i32gather_epi32/ _mm256_mask_i32gather_epi32
_mm_i32gather_epi32/ _mm256_i32gather_epi32
_mm_mask_i32gather_epi64/ _mm256_mask_i32gather_epi64
_mm_i32gather_epi64/ _mm256_i32gather_epi64
_mm_mask_i64gather_epi32/ _mm256_mask_i64gather_epi32
_mm_i64gather_epi32/ _mm256_i64gather_epi32
_mm_mask_i64gather_epi64/ _mm256_mask_i64gather_epi64
_mm_i64gather_epi64/ _mm256_i64gather_epi64
Intrinsics for Logical Shift Operations
_mm256_sll_epi16/32/64
_mm256_slli_epi16/32/64
_mm256_sllv_epi32/64
_mm_sllv_epi32/64
_mm256_slli_si256
_mm256_srli_si256
_mm256_srl_epi16/32/64
_mm256_srli_epi16/32/64
_mm256_srlv_epi32/64
_mm_srlv_epi32/64
Intrinsics for Insert/Extract Operations
_mm256_inserti128_si256
_mm256_extracti128_si256
Intrinsics for Masked Load/Store Operations
_mm_maskload_epi32/64/ _mm256_maskload_epi32/64
_mm_maskstore_epi32/64/ _mm256_maskstore_epi32/64
Intrinsics for Miscellaneous Operations
_mm256_alignr_epi8
_mm256_movemask_epi8
_mm256_stream_load_si256
Intrinsics for Operations to Manipulate Integer Data at Bit-Granularity
_bextr_u32/64
_blsi_u32/64
_blsmsk_u32/64
_blsr_u32/64
_bzhi_u32/64
_pext_u32/64
_pdep_u32/64
_lzcnt_u32/64
_tzcnt_u32/64
Intrinsics for Pack/Unpack Operations
_mm256_packs_epi16/32
_mm256_packus_epi16/32
_mm256_unpackhi_epi8/16/32/64
_mm256_unpacklo_epi8/16/32/64
Intrinsics for Packed Move with Extend Operations
_mm256_cvtepi8_epi16/32/64
_mm256_cvtepi16_epi32/64
_mm256_cvtepi32_epi64
_mm256_cvtepu8_epi16/32/64
_mm256_cvtepu16_epi32/64
_mm256_cvtepu32_epi64
Intrinsics for Permute Operations
_mm256_permutevar8x32_epi32
_mm256_permutevar8x32_ps
_mm256_permute4x64_epi64
_mm256_permute4x64_pd
_mm256_permute2x128_si256
Intrinsics for Shuffle Operations
_mm256_shuffle_epi8
_mm256_shuffle_epi32
_mm256_shufflehi_epi16
_mm256_shufflelo_epi16
Intrinsics for Intel® Transactional Synchronization Extensions (Intel® TSX)
Overview
Programming Considerations
Restricted Transactional Memory Intrinsics
RTM Overview
_xtest
_xbegin
_xend
_xabort
Hardware Lock Elision Intrinsics (Windows*)
HLE Overview (Windows*)
Acquire _InterlockedCompareExchange Functions (Windows*)
Acquire _InterlockedExchangeAdd Functions (Windows*)
Release _InterlockedCompareExchange Functions (Windows*)
Release _InterlockedExchangeAdd Functions (Windows*)
Release _Store Functions (Windows*)
Function Prototypes and Macro Definitions (Windows*)
Intrinsics for Intel® Advanced Vector Extensions
Overview
Details of Intel® AVX Intrinsics and FMA Intrinsics
Intrinsics for Arithmetic Operations
_mm256_add_pd
_mm256_add_ps
_mm256_addsub_pd
_mm256_addsub_ps
_mm256_hadd_pd
_mm256_hadd_ps
_mm256_sub_pd
_mm256_sub_ps
_mm256_hsub_pd
_mm256_hsub_ps
_mm256_mul_pd
_mm256_mul_ps
_mm256_div_pd
_mm256_div_ps
_mm256_dp_ps
_mm256_sqrt_pd
_mm256_sqrt_ps
_mm256_rsqrt_ps
_mm256_rcp_ps
Intrinsics for Bitwise Operations
_mm256_and_pd
_mm256_and_ps
_mm256_andnot_pd
_mm256_andnot_ps
_mm256_or_pd
_mm256_or_ps
_mm256_xor_pd
_mm256_xor_ps
Intrinsics for Blend and Conditional Merge Operations
_mm256_blend_pd
_mm256_blend_ps
_mm256_blendv_pd
_mm256_blendv_ps
Intrinsics for Compare Operations
_mm_cmp_pd, _m256_cmp_pd
_mm_cmp_ps, _m256_cmp_ps
_mm_cmp_sd
_mm_cmp_ss
Intrinsics for Conversion Operations
_mm256_cvtepi32_pd
_mm256_cvtepi32_ps
_mm256_cvtpd_epi32
_m256_cvtps_epi32
_mm256_cvtpd_ps
_m256_cvtps_pd
_mm256_cvttp_epi32
_mm256_cvttps_epi32
Intrinsics to Determine Maximum and Minimum Values
_mm256_max_pd
_mm256_max_ps
_mm256_min_pd
_mm256_min_ps
Intrinsics for Load and Store Operations
_mm256_broadcast_pd
_mm256_broadcast_ps
_mm256_broadcast_sd
_mm256_broadcast_ss, _mm_broadcast_ss
_mm256_load_pd
_mm256_load_ps
_mm256_load_si256
_mm256_loadu_pd
_mm256_loadu_ps
_mm256_loadu_si256
_mm256_maskload_pd, _mm_maskload_pd
_mm256_maskload_ps, _mm_maskload_ps
_mm256_store_pd
_mm256_store_ps
_mm256_store_si256
_mm256_storeu_pd
_mm256_storeu_ps
_mm256_storeu_si256
_mm256_stream_pd
_mm256_stream_ps
_mm256_stream_si256
_mm256_maskstore_pd, _mm_maskstore_pd
_mm256_maskstore_ps, _mm_maskstore_ps
Intrinsics for Miscellaneous Operations
_mm256_extractf128_pd
_mm256_extractf128_ps
_mm256_extractf128_si256
_mm256_insertf128_pd
_mm256_insertf128_ps
_mm256_insertf128_si256
_mm256_lddqu_si256
_mm256_movedup_pd
_mm256_movehdup_ps
_mm256_moveldup_ps
_mm256_movemask_pd
_mm256_movemask_ps
_mm256_round_pd
_mm256_round_ps
_mm256_set_pd
_mm256_set_ps
_mm256_set_epi32
_mm256_setr_pd
_mm256_setr_ps
_mm256_setr_epi32
_mm256_set1_pd
_mm256_set1_ps
_mm256_set1_epi32
_mm256_setzero_pd
_mm256_setzero_ps
_mm256_setzero_si256
_mm256_zeroall
_mm256_zeroupper
Intrinsics for Packed Test Operations
_mm256_testz_si256
_mm256_testc_si256
_mm256_testnzc_si256
_mm256_testz_pd, _mm_testz_pd
_mm256_testz_ps, _mm_testz_ps
_mm256_testc_pd, _mm_testc_pd
_mm256_testc_ps, _mm_testc_ps
_mm256_testnzc_pd, _mm_testnzc_pd
_mm256_testnzc_ps, _mm_testnzc_ps
Intrinsics for Permute Operations
_mm256_permute_pd, _mm_permute_pd
_mm256_permute_ps
_mm256_permutevar_pd, _mm_permutevar_pd
_mm256_permutevar_ps
_mm256_permute2f128_pd
_mm256_permute2f128_ps
_mm256_permute2f128_si256
Intrinsics for Shuffle Operations
_mm256_shuffle_pd
_mm256_shuffle_ps
Intrinsics for Unpack and Interleave Operations
_mm256_unpackhi_pd
_mm256_unpackhi_ps
_mm256_unpacklo_pd
_mm256_unpacklo_ps
Support Intrinsics for Vector Typecasting Operations
_mm256_castpd_ps
_mm256_castps_pd
_mm256_castpd_si256
_mm256_castps_si256
_mm256_castsi256_pd
_mm256_castsi256_ps
_mm256_castpd128_pd256
_mm256_castpd256_pd128
_mm256_castps128_ps256
_mm256_castps256_ps128
_mm256_castsi128_si256
_mm256_castsi256_si128
Intrinsics Generating Vectors of Undefined Values
_mm256_undefined_ps()
_mm256_undefined_pd()
_mm256_undefined_si128()
Intrinsics for Intel® Streaming SIMD Extensions 4
Overview
Efficient Accelerated String and Text Processing
Overview
Packed Compare Intrinsics
Application Targeted Accelerators Intrinsics
Vectorizing Compiler and Media Accelerators
Overview: Vectorizing Compiler and Media Accelerators
Packed Blending Intrinsics
Floating Point Dot Product Intrinsics
Packed Format Conversion Intrinsics
Packed Integer Min/Max Intrinsics
Floating Point Rounding Intrinsics
DWORD Multiply Intrinsics
Register Insertion/Extraction Intrinsics
Test Intrinsics
Packed DWORD to Unsigned WORD Intrinsic
Packed Compare for Equal Intrinsic
Cacheability Support Intrinsic
Intrinsics for Intel® Supplemental Streaming SIMD Extensions 3
Overview
Addition Intrinsics
Subtraction Intrinsics
Multiplication Intrinsics
Absolute Value Intrinsics
Shuffle Intrinsics
Concatenate Intrinsics
Negation Intrinsics
Intrinsics for Intel® Streaming SIMD Extensions 3
Overview
Integer Vector Intrinsics
Single-precision Floating-point Vector Intrinsics
Double-precision Floating-point Vector Intrinsics
Miscellaneous Intrinsics
Macro Functions
Intrinsics for Intel® Streaming SIMD Extensions 2
Overview
Floating-point Intrinsics
Arithmetic Intrinsics
Logical Intrinsics
Compare Intrinsics
Conversion Intrinsics
Load Intrinsics
Set Intrinsics
Store Intrinsics
Integer Intrinsics
Arithmetic Intrinsics
Logical Intrinsics
Shift Intrinsics
Compare Intrinsics
Conversion Intrinsics
Move Intrinsics
Load Intrinsics
Set Intrinsics
Store Intrinsics
Miscellaneous Functions and Intrinsics
Cacheability Support Intrinsics
Miscellaneous Intrinsics
Casting Support Intrinsics
Pause Intrinsic
Macro Function for Shuffle
Intrinsics Returning Vectors of Undefined Values
Intrinsics for Intel® Streaming SIMD Extensions
Overview
Details about Intel® Streaming SIMD Extension Intrinsics
Writing Programs with Intel® Streaming SIMD Extensions Intrinsics
Arithmetic Intrinsics
Logical Intrinsics
Compare Intrinsics
Conversion Intrinsics
Load Intrinsics
Set Intrinsics
Store Intrinsics
Cacheability Support Intrinsics
Integer Intrinsics
Intrinsics to Read and Write Registers
Miscellaneous Intrinsics
Macro Functions
Macro Function for Shuffle Operations
Macro Functions to Read and Write Control Registers
Macro Function for Matrix Transposition
Intrinsics for MMX™ Technology
Overview
Details about MMX™ Technology Intrinsics
The EMMS Instruction: Why You Need It
EMMS Usage Guidelines
General Support Intrinsics
Packed Arithmetic Intrinsics
Shift Intrinsics
Logical Intrinsics
Compare Intrinsics
Set Intrinsics
Intrinsics for Advanced Encryption Standard Implementation
Overview
Intrinsics for Carry-less Multiplication Instruction and Advanced Encryption Standard Instructions
Intrinsics for Converting Half Floats
Overview
Intrinsics for Converting Half Floats
Intrinsics for Short Vector Math Library Operations
Overview
Intrinsics for Division Operations
_mm_div_epi8/ _mm256_div_epi8
_mm_div_epi16/ _mm256_div_epi16
_mm_div_epi32/ _mm256_div_epi32
_mm_div_epi64/ _mm256_div_epi64
_mm_div_epu8/ _mm256_div_epu8
_mm_div_epu16/ _mm256_div_epu16
_mm_div_epu32/ _mm256_div_epu32
_mm_div_epu64/ _mm256_div_epu64
_mm_rem_epi8/ _mm256_rem_epi8
_mm_rem_epi16/ _mm256_rem_epi16
_mm_rem_epi32/ _mm256_rem_epi32
_mm_rem_epi64/ _mm256_rem_epi64
_mm_rem_epu8/ _mm256_rem_epu8
_mm_rem_epu16/ _mm256_rem_epu16
_mm_rem_epu32/ _mm256_rem_epu32
_mm_rem_epu64/ _mm256_rem_epu64
Intrinsics for Error Function Operations
_mm_cdfnorminv_pd, _mm256_cdfnorminv_pd
_mm_cdfnorminv_ps, _mm256_cdfnorminv_ps
_mm_erf_pd, _mm256_erf_pd
_mm_erf_ps, _mm256_erf_ps
_mm_erfc_pd, _mm256_erfc_pd
_mm_erfc_ps, _mm256_erfc_ps
_mm_erfinv_pd, _mm256_erfinv_pd
_mm_erfinv_ps, _mm256_erfinv_ps
Intrinsics for Exponential Operations
_mm_exp2_pd, _mm256_exp2_pd
_mm_exp2_ps, _mm256_exp2_ps
_mm_exp_pd, _mm256_exp_pd
_mm_exp_ps, _mm256_exp_ps
_mm_exp10_pd, _mm256_exp10_pd
_mm_exp10_ps, _mm256_exp10_ps
_mm_expm1_pd, _mm256_expm1_pd
_mm_expm1_ps, _mm256_expm1_ps
_mm_cexp_ps, _mm256_cexp_ps
_mm_pow_pd, _mm256_pow_pd
_mm_pow_ps, _mm256_pow_ps
_mm_hypot_pd _mm256_hypot_pd
_mm_hypot_ps _mm256_hypot_ps
Intrinsics for Logarithmic Operations
_mm_log2_pd, _mm256_log2_pd
_mm_log2_ps, _mm256_log2_ps
_mm_log10_pd, _mm256_log10_pd
_mm_log10_ps, _mm256_log10_ps
_mm_log_pd, _mm256_log_pd
_mm_log_ps, _mm256_log_ps
_mm_logb_pd, _mm256_logb_pd
_mm_logb_ps, _mm256_logb_ps
_mm_log1p_pd, _mm256_log1p_pd
_mm_log1p_ps, _mm256_log1p_ps
_mm_clog_ps, _mm256_clog_ps
Intrinsics for Square Root and Cube Root Operations
_mm_sqrt_pd, _mm256_sqrt_pd
_mm_sqrt_ps, _mm256_sqrt_ps
_mm_invsqrt_pd, _mm256_invsqrt_pd
_mm_invsqrt_ps, _mm256_invsqrt_ps
_mm_cbrt_pd, _mm256_cbrt_pd
_mm_cbrt_ps, _mm256_cbrt_ps
_mm_invcbrt_pd, _mm256_invcbrt_pd
_mm_invcbrt_ps, _mm256_invcbrt_ps
_mm_csqrt_ps, _mm256_csqrt_ps
Intrinsics for Trigonometric Operations
_mm_acos_pd, _mm256_acos_pd
_mm_acos_ps, _mm256_acos_ps
_mm_acosh_pd, _mm256_acosh_pd
_mm_acosh_ps, _mm256_acosh_ps
_mm_asin_pd, _mm256_asin_pd
_mm_asin_ps, _mm256_asin_ps
_mm_asinh_pd, _mm256_asinh_pd
_mm_asinh_ps, _mm256_asinh_ps
_mm_atan_pd, _mm256_atan_pd
_mm_atan_ps, _mm256_atan_ps
_mm_atan2_pd, _mm256_atan2_pd
_mm_atan2_ps, _mm256_atan2_ps
_mm_atanh_pd, _mm256_atanh_pd
_mm_atanh_ps, _mm256_atanh_ps
_mm_cos_pd, _mm256_cos_pd
_mm_cos_ps, _mm256_cos_ps
_mm_cosd_pd, _mm256_cosd_pd
_mm_cosd_ps, _mm256_cosd_ps
_mm_cosh_pd, _mm256_cosh_pd
_mm_cosh_ps, _mm256_cosh_ps
_mm_sin_pd, _mm256_sin_pd
_mm_sin_ps, _mm256_sin_ps
_mm_sind_pd, _mm256_sind_pd
_mm_sind_ps, _mm256_sind_ps
_mm_sinh_pd, _mm256_sinh_pd
_mm_sinh_ps, _mm256_sinh_ps
_mm_tan_pd, _mm256_tan_pd
_mm_tan_ps, _mm256_tan_ps
_mm_tand_pd, _mm256_tand_pd
_mm_tand_ps, _mm256_tand_ps
_mm_tanh_pd, _mm256_tanh_pd
_mm_tanh_ps, _mm256_tanh_ps
_mm_sincos_pd, _mm256_sincos_pd
_mm_sincos_ps, _mm256_sincos_ps
Libraries
Creating Libraries
Overview: Using Libraries
Using Intel Shared Libraries
Using Shared Libraries on OS X*
Managing Libraries
Redistributing Libraries When Deploying Applications
Intel C++ Class Libraries
Introduction to the Class Libraries
Overview: Intel® C++ Class Libraries
Hardware and Software Requirements
Details About the Libraries
C++ Classes and SIMD Operations
Capabilities of C++ SIMD Classes
Integer Vector Classes
Overview: Integer Vector Classes
Terms, Conventions, and Syntax Defined
Rules for Operators
Assignment Operator
Logical Operators
Addition and Subtraction Operators
Multiplication Operators
Shift Operators
Comparison Operators
Conditional Select Operators
Debug Operations
Unpack Operators
Pack Operators
Clear MMX™ State Operator
Integer Functions for Streaming SIMD Extensions
Conversions between Fvec and Ivec
Floating-point Vector Classes
Overview: Floating-point Vector Classes
Fvec Notation Conventions
Data Alignment
Conversions
Constructors and Initialization
Arithmetic Operators
Minimum and Maximum Operators
Logical Operators
Compare Operators
Conditional Select Operators for Fvec Classes
Cacheability Support Operators
Debug Operations
Load and Store Operators
Unpack Operators
Move Mask Operators
Classes Quick Reference
Programming Example
C++ Library Extensions
Introduction
Intel's valarray implementation
Introduction to Intel's valarray Implementation
Using Intel's valarray Implementation
Libraries for Intel® Many Integrated Core Architecture (Intel® MIC Architecture)
Introducing Libraries for Intel® MIC Architecture
About Libraries for Intel® MIC Architecture
Use of C++ Classes for SIMD Operations on Intel® MIC Architecture
Programming Example
Intel's C++ Asynchronous I/O Extensions for Windows* OS
Overview
Intel's C++ Asynchronous I/O Library for Windows* OS
Overview
aio_read
aio_write
Example for aio_read and aio_write Functions
aio_suspend
Example for aio_suspend Function
aio_error
aio_return
Example for aio_error and aio_return Functions
aio_fsync
aio_cancel
Example for aio_cancel Function
lio_listio
Example for lio_listio Function
Handling Errors Caused by Asynchronous I/O Functions
Intel's C++ Asynchronous I/O Class for Windows* OS
Overview
Template Class async_class
get_last_operation_id
wait
get_status
get_last_error
get_error_operation_id
stop_queue
resume_queue
clear_queue
Example for Using async_class Template Class
Macros
ISO Standard Predefined Macros
Additional Predefined Macros
Pragmas
Overview: Intel® C++ Compiler Pragmas
Intel-specific Pragmas
Intel-specific Pragma Reference
alloc_section
cilk grainsize
distribute_point
inline/noinline/forceinline
inline-max-per-routine
inline-max-total-size
intel_omp_task
intel_omp_taskq
ivdep
loop_count
nofusion
novector
offload
offload_attribute
offload_transfer
offload_wait
omp atomic
omp barrier
omp critical
omp declare simd
omp declare target
omp distribute
omp flush
omp for
omp for simd
omp master
omp ordered
omp parallel
omp parallel for
omp parallel for simd
omp parallel sections
omp sections
omp simd
omp single
omp target
omp target data
omp target update
omp task
omp taskgroup
omp taskwait
omp taskyield
omp teams
omp threadprivate
optimize
optimization_level
optimization_parameter
parallel noparallel
parallel_loop
prefetch/noprefetch
simd
unroll nounroll
unroll_and_jam nounroll_and_jam
unused
vector
Intel-supported Pragmas
Error Handling
Remarks, Warnings, and Errors